Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
نویسنده
چکیده
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
منابع مشابه
Test Planning for 3D Stacked ICs with Through-Silicon Vias
Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorit...
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Through-Silicon Vias (TSVs) provide high-density, low-latency, and low-power vertical interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5Dand 3D-Stacked ICs. In 2.5D-SICs, multiple dies are stacked side-by-side on top of a passive silicon interposer base containing TSVs. 3D-SICs are towers of vertically stacked active dies, in which the vertical inter-die ...
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In the race against Moores Law, integrated chips (ICs) with multiple dies stacked over one another and connected by ThroughSilicon Vias (TSVs), called 3D TSV-Stacked ICs (SICs) have attracted a fair amount of research [1]–[5]. Due to imperfections in IC manufacturing, each individual chip must be tested. Testing each IC, increases cost, which is highly related to the testing time spent on each ...
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TSV-based 3D-SICs significantly impact core-based systemon-chip (SOC) design. Testing of core-based dies in 3D-SICs introduces new challenges [1], [2]. In order to test the dies in a stack, the embedded cores, and the TSVs, a test access mechanism (TAM) must be included on the die to transport test data to the cores, and a 3D TAM is needed to transfer test data to the die from the stack input/o...
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Test planning for core-based 3D stacked ICs under power constraint is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-sta...
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